Fully parameterized, reusable FPGA IP library for Software Defined Radio
A fully parameterized, reusable FPGA IP library for Software Defined Radio (SDR) applications, targeting Xilinx/AMD and Intel/Altera FPGAs. Primary uses in Mintaka AI powered developent process as reusable fully parametrized IP library.
All RTL is written in SystemVerilog IEEE 1800-2017. Every module uses AXI4-Stream as the standard data transport interface, making modules composable without glue logic.
The library covers the complete SDR signal chain — from ADC/DAC interfaces through DDC/DUC, filtering, synchronization, modulation/demodulation, FEC, and packet processing — plus supporting infrastructure (CDC, memory, control plane, debug).
| Group | Path | Files | Description |
|---|---|---|---|
| Packages | rtl/pkg/ | 3 | Shared types, parameters, AXI-Stream interface — compile first |
| Fixed-Point | rtl/fixed_point/ | 8 | Resize, round, saturate, clip detect, gain, shift |
| Complex Math | rtl/complex/ | 8 | Add, subtract, multiply, conjugate, abs², scale, rotate, mix |
| NCO / DDS | rtl/nco/ | 22 | Phase accumulator, LUT-based and CORDIC-based DDS, complex NCO, GNSS NCO |
| CORDIC | rtl/cordic/ | 6 | sin/cos, atan2, vectoring, rotation, polar↔cartesian |
| Filters | rtl/filters/ | 31 | FIR (direct, symmetric, polyphase, reloadable), CIC, halfband, boxcar, GNSS |
| DDC | rtl/ddc/ | 4 | Digital Down Converter chain: mixer → CIC → FIR → baseband IQ |
| DUC | rtl/duc/ | 3 | Digital Up Converter chain: baseband IQ → FIR → CIC → mixer |
| Sync / AGC | rtl/sync/agc/ | 5 | Power estimator, RSSI, AGC loop, gain apply, saturator |
| Sync / Carrier | rtl/sync/carrier/ | 6 | Costas loop (BPSK/QPSK), complex PLL, freq/phase error estimators |
| Sync / Timing | rtl/sync/timing/ | 5 | Gardner TED, Mueller-Müller, symbol timing loop, fractional delay |
| Sync / Frame | rtl/sync/frame/ | 5 | Preamble correlator, sync word detector, frame aligner, packet detector |
| Modulation | rtl/modulation/ | 9 | BPSK, QPSK, OQPSK, OOK, FSK, GFSK, GMSK, QAM16, QAM64 |
| Demodulation | rtl/demodulation/ | 15 | Demodulators + LLR/soft-decision output for all modulation schemes |
| FFT | rtl/fft/ | 16 | Radix-2 and streaming FFT/IFFT, windowing, power spectrum, peak detect |
| Channelizer | rtl/channelizer/ | 5 | Polyphase filter bank, FFT channelizer, channel select |
| OFDM | rtl/ofdm/ | 10 | CP insert/remove, FFT RX/TX, pilot extraction, channel estimation, equalizer |
| FEC | rtl/fec/ | 14 | CRC, scrambler, convolutional encoder, Viterbi, Reed-Solomon, LDPC, Polar |
| Packet | rtl/packet/ | 9 | Framer, deframer, header parser, CRC append/verify, stream packetizer |
| Stream | rtl/stream/ | 10 | FIFO, register slice, width converter, rate adapter, mux, demux, splitter |
| CDC | rtl/cdc/ | 10 | Async FIFO, pulse/level/bus sync, gray counter, reset synchronizer |
| Memory | rtl/memory/ | 9 | Single/dual/true-dual-port RAM, ROM LUT, delay line, circular buffer |
| Interfaces | rtl/interfaces/ | 12 | ADC/DAC capture/output, IQ formatter, JESD204, LVDS, SPI RF control |
| Control | rtl/control/ | 8 | Register bank, AXI-Lite slave, Wishbone slave, SPI/UART/I2C register I/F |
| Debug | rtl/debug/ | 12 | ILA wrapper, stream monitor, overflow/underflow counters, IQ capture buffer |
| UART | rtl/uart/ | 3 | UART TX, RX, and loopback modules |
kCamelCase prefix (e.g. kDataWidth)snake_case; AXI-Stream slave = s_*, master = m_*rst_n), synchronous releasesdr_types_pkg; use logic, never wire/regThis library is accessible via an MCP (Model Context Protocol) server for AI-assisted design. The server provides read-only access to all RTL modules and testbenches.
| Tool | Parameters | Description |
|---|---|---|
list_groups | — | List all module groups with file counts |
list_modules | group? | List modules, optionally filtered by group |
get_module_code | module_name | Get full SystemVerilog source of a module |
search_modules | query | Search modules by name or description |
get_module_info | module_name | Get metadata: path, group, size, parameters |
list_testbenches | group? | List testbench files, optionally by group |
get_filelist | — | Get the master filelist (sdr_lib.f) content |
The MCP server exposes RTL code as read-only resources. Modules are used in designs without modification.